A semiconductor integrated circuit contains many layers of different materials usually classified according to whether the layer is a semiconductor, a dielectric (electrical insulator) or metal. However, some materials such as barrier materials, for example, TiN, are not so easily classified. The two principal current means of depositing metals and barrier materials are sputtering, also referred to as physical vapor deposition (PVD), and chemical vapor deposition (CVD). Of the two, sputtering has the inherent advantages of low cost source material and high deposition rates. However, sputtering has an inherent disadvantage when a material needs to be filled into a deep narrow hole, that is, one having a high aspect ratio. The same disadvantage obtains when a thin layer of the material needs to be coated onto the sides of the hole, which is often required for barrier materials. Aspect ratios of 3:1 present challenges, 5:1 becomes difficult, 8:1 is becoming a requirement, and 10:1 and greater are expected in the future. Sputtering itself is fundamentally a nearly isotropic process producing ballistic sputter particles which do not easily reach the bottom of deep narrow holes. On the other hand, CVD tends to be a conformal process equally effective at the bottom of holes and on exposed top planar surfaces.
Up until the recent past, aluminum has been the metal of choice for the metallization used in horizontal interconnects and in the vias connecting two levels of metallization. In more recent technology, copper vias extend between two levels of horizontal copper interconnects. Contacts to the underlying silicon present a larger problem, but may still be accomplished with either aluminum or copper. Copper interconnects are used to reduce signal delay in advanced ULSI circuits. It is understood that copper may be pure copper or a copper alloy containing up to 10% alloying with other elements such as magnesium and aluminum. Due to continued downward scaling of the critical dimensions of microcircuits, critical electrical parameters of integrated circuits, such as contact and via resistances, have become more difficult to achieve. In addition, due to the smaller dimensions, the aspect ratios of inter-metal features such as contacts and vias are also increasing. An advantage of copper is that it may be quickly and inexpensively deposited by electrochemical processes, such as electroplating. However, sputtering or possibly CVD of thin copper layers onto the walls of via holes is still considered necessary to act as an electrode for electroplating or as a seed layer for the electroplated copper. The discussion of copper processes will be delayed until later.
The conventional sputter reactor has a planar target in parallel opposition to the wafer being sputter deposited. A negative DC voltage is applied to the target of magnitude sufficient to ionize the argon working gas into a plasma. The positive argon ions are attracted to the negatively charged target with sufficient energy to sputter atoms of the target material. Some of the sputtered atoms strike the wafer and form a sputter coating thereon. Most usually, a magnetron is positioned in back of the target to create a larger magnetic field adjacent to the target. The magnetic field traps electrons, and, to maintain charge neutrality in the plasma, the ion density also increases. As a result, the plasma density and sputter rate are increased. The conventional magnetron generates a magnetic field lying principally parallel to the target.
Much effort has been expended to allow sputtering to effectively coat metals and barrier materials deep into narrow holes. High-density plasma (HDP) sputtering has been developed in which the argon working gas is excited into a high-density plasma, which is defined as a plasma having an ionization density of at least 1011 cm−3 across the entire space the plasma fills except the plasma sheath. Typically, an HDP sputter reactor uses an RF power source connected to an inductive coil adjacent to the plasma region to generate the high-density plasma. The high argon ion density causes a significant fraction of sputtered atoms to be ionized. If the pedestal electrode supporting the wafer being sputter coated is negatively electrically biased, the ionized sputter particles (metal ions) are accelerated toward the wafer to form a directional column that reaches deeply into narrow holes.
HDP sputter reactors, however, have disadvantages. They involve a somewhat new technology and are relatively expensive. Furthermore, the quality of the sputtered films they produce is often not the best, typically having an undulatory surface. Also, high-energy ions, particularly the argon ions which are also attracted to the wafer, tend to damage the material already deposited.
Another sputtering technology, referred to as self-ionized plasma (SIP) sputtering, has been developed to fill deep holes. See, for example, U.S. patent application Ser. No. 09/373,097 filed Aug. 12, 1999 by Fu, now issued as U.S. Pat. No. 6,183,614, and U.S. patent application Ser. No. 09/414,614 filed Oct. 8, 1999 by Chiang et al, now issued as U.S. Pat. No. 6,398,929. Both of these patent applications are incorporated by reference in their entireties. In its original implementations, SIP relies upon a somewhat standard capacitively coupled plasma sputter reactor having a planar target in parallel opposition to the wafer being sputter coated and a magnetron positioned in back of the target to increase the plasma density and hence the sputtering rate. The SIP technology, however, is characterized by a high target power density, a small magnetron, and a magnetron having an outer magnetic pole piece enclosing an inner magnetic pole piece with the outer pole piece having a significantly higher total magnetic flux than the inner pole piece. In some implementations, the target is separated from the wafer by a large distance to effect long-throw sputtering, which enhances collimated sputtering. The asymmetric magnetic pole pieces causes the magnetic field to have a significant vertical component extending far towards the wafer, thus enhancing and extending the high-density plasma volume and promoting transport of ionized sputter particles.
The SIP technology was originally developed for sustained self-sputtering (SSS) in which a sufficiently high number of sputter particles are ionized that they may be used to further sputter the target and no argon working gas is required. Of the metals commonly used in semiconductor fabrication, only copper has a sufficiently high self-sputtering yield to allow sustained self-sputtering.
The extremely low pressures and relatively high ionization fractions associated with SSS are advantageous for filling deep holes with copper. However, it was quickly realized that the SIP technology could be advantageously applied to the sputtering of aluminum and other metals and even to copper sputtering at moderate pressures. SIP sputtering produces high quality films exhibiting high hole filling factors regardless of the material being sputtered.
Nonetheless, SIP has some disadvantages. The small area of the magnetron may require circumferential scanning of the magnetron in a rotary motion at the back of the target to achieve even a minimal level of uniformity, and even with rotary scanning, radial uniformity is difficult to achieve. Furthermore, very high target powers have been required in the previously known versions of SIP. High-capacity power supplies are expensive and necessitate complicated target cooling. Lastly, known versions of SIP tend to produce a relatively low ionization fraction of sputter particles, for example, 20%. The remaining non-ionized fraction of sputtered particles has a relatively isotropic distribution rather than forming a forward directed column which results from metal ions being accelerated toward a biased wafer. Also, the target diameter in a typical commercial sputter reactor is only slightly greater than the wafer diameter. As a result, those holes being coated located at the edge of the wafer have radially outer sidewalls which see a larger fraction of the target and are more heavily coated than the radially inner sidewalls. Therefore, the sidewalls of the edge holes are asymmetrically coated.
Other sputter geometries have been developed which increase the ionization density. One example is a multi-pole hollow cathode target, several variants of which are disclosed by Barnes et al. in U.S. Pat. No. 5,178,739. Its target has a hollow cylindrical shape, usually closed with a circular back wall, and is electrically biased. Typically, a series of magnets, positioned on the sides of the cylindrical cathode of alternating magnetic polarization, create a magnetic field extending generally parallel to the cylindrical sidewall.
Another approach uses a pair of facing targets facing the lateral sides of the plasma space above the wafer. Such systems are described, for example, by Kitamoto et al. in “Compact sputtering apparatus for depositing Co—Cr alloy thin films in magnetic disks,” Proceedings: The Fourth International Symposium on Sputtering & Plasma Processes, Kanazawa, Japan, Jun. 4–6, 1997, pp. 519–522, by Yamazato et al. in “Preparation of TiN thin films by facing targets magnetron sputtering, ibid., pp. 635–638, and by Musil et al. in “Unbalanced magnetrons and new sputtering systems with enhanced plasma ionization,” Journal of Vacuum Science and Technology A, vol. 9, no. 3, May 1991, pp. 1171–1177. The facing pair geometry has the disadvantage that the magnets are stationary and create a horizontally extending field that is inherently non-uniform with respect to the wafer.
Musil et al., ibid., pp. 1174, 1175 describe a coil-driven magnetic mirror magnetron having a central post of one magnetic polarization and surrounding rim of another polarization. An annular vault-shaped target is placed between the post and rim. This structure has the disadvantage that the soft magnetic material forming the two poles, particularly the central spindle, are exposed to the plasma during sputtering and inevitably contaminate the sputtered layer. Furthermore, the coil drive provides a substantially cylindrical geometry, which may not be desired in some situations. Also, the disclosure illustrates a relatively shallow geometry for the target vault, which does not take advantage of some possible beneficial effects for a concavely shaped target.
Helmer et al. in U.S. Pat. No. 5,482,611 describe a target having a groove or vault facing the substrate. Stationary magnets are arranged on the outside of the vault sidewalls with parallel magnetic polarities so as to create a magnetic field generally parallel to the vault walls within the vault and having a magnetic cusp or null spot near the opening of the vault. The magnetic cusp directs the metal sputter ions in a beam towards the wafer. However, Helmer et al. admit that uniformity of deposition with this magnetic configuration is not good. Lantsman in U.S. Pat. No. 5,589,041 discloses an plasma etch chamber having a dielectric roof that is formed with a vault so as to shape the plasma.
It is thus desired to combine many of the good benefits of the different plasma sputter reactors described above while avoiding their separate disadvantages.
Returning now to copper processing and the structures that need to be formed for copper vias, as is well known to those in the art, in a typical copper interconnect process flow, a thin barrier layer is first deposited onto the walls of the via hole prior to the copper deposition. The barrier layer prevents copper from diffusing into the insulating dielectric layer separating the two copper levels and also to prevent intra metal and inter metal electrical shorts. A typical barrier for copper over silicon oxide includes Ta or TaN or a combination thereof, but other materials have been proposed, such as W/WN and Ti/TiN among others. In a typical barrier deposition process, the barrier layer is deposited using PVD or other method to form a continuous layer between the underlying and overlying copper layers including the contact area at the bottom of the via hole. Thin layers of these barrier materials have a small but finite transverse resistance. A structure resulting from this copper interconnect process produces a contact having a finite characteristic resistance (known in the art as a contact or via resistance) that depends on the geometry. Conventionally, the barrier layer at the bottom of the contact or via hole contributes about 30% of the total contact or via resistance. Geffken et al. disclose in U.S. Pat. No. 5,985,762 a separate directional etching step to remove the barrier layer from the bottom of the via hole over an underlying copper feature but not from the via sidewalls so that, during the sputter removal of the copper oxide at the via bottom, the dielectric is not poisoned by the sputtered copper. This process requires presumably a separate etching chamber. Furthermore, the process deleteriously also removes the barrier at the bottom of the trench in a dual-damascene structure. They accordingly deposit another conformal barrier layer, which remains under the metallized via.
As a result, there is a need in the art for a method and apparatus to form a low-resistance contact between underlying and overlying copper layers and having a low contact resistance without unduly complicating the process.
A copper layer used to form an interconnect is conveniently deposited by electrochemical deposition, for example, electroplating. As is well known, an adhesion or seed layer of copper is usually required to nucleate an ensuing electrochemical deposition on the dielectric sidewalls as well as to provide a current path for the electroplating. In a typical deposition process, the copper seed layer is deposited using PVD or CVD methods, and the seed layer is typically deposited on top of the barrier layer. A typical barrier/seed layer deposition sequence also requires a pre-clean step to remove native oxide and other contaminants that reside on the underlying metal that has been previously exposed in etching the via hole. The pre-clean step, for example, a sputter etch clean step using an argon plasma, is typically performed in a process chamber that is separate from the PVD chamber used to deposit the barrier and seed layers. With shrinking dimension of the integrated circuits, the efficacy of the pre-clean step, as well as sidewall coverage of the seed layer within the contact/via feature, become more problematical.
As a result, the art needs a method and apparatus that improves the pre-clean and deposition of the seed layer. Further, the seed layer needs to be conformally deposited in all portions of the via hole even if the barrier layer is removed in portions of the hole.